Semiconductor device and manufacturing  method thereof

ABSTRACT

A semiconductor device has a first insulation film defining a plurality of contact holes arranged along a predetermined direction. A plurality of first contact plugs is respectively formed in the contact holes. A second insulation film is formed on the first insulation film and defining an opening to expose a predetermined region of the first insulation film including a region where the first contact plugs are formed. A plurality of interconnections are formed to extend across the opening and to be in contact with top surfaces of the first contact plugs, respectively.

This application is based upon and claims the benefit of priority fromJapanese patent application No. 2009-078001, filed on Mar. 27, 2009, thedisclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

This invention relates to a semiconductor device and a manufacturingmethod thereof, and particularly relates to a semiconductor devicehaving interconnections connected to contact plugs arranged in array anda manufacturing method of such a semiconductor device.

As high integration of MOS integrated circuits has been rapidlyprogressed, elements are now formed by using fine-pattern technology toits utmost limit. Under such circumstances, there are demands infabrication of integrated circuits that holes be formed to have as smalla diameter as possible and as small a hole-to-hole distance as possibleaccording to available lithography techniques.

Element structures requiring formation of holes include those in whichinterconnections are connected to contact plugs the top of which arecovered with an insulation film. Specifically, holes are opened in theinsulation film covering the contact plugs, and electrical connection isestablished between the contact plugs and the interconnections formed onthe insulation film, for example by filling the holes with a conductivematerial.

Conventionally, these holes are formed in one-to-one relationship to thecontact plugs. (This type of technology is described for example inJapanese Laid-Open Patent Publication No. 2007-287794). Therefore, whena plurality of contact plugs are formed in a high density, holescorresponding to thereto must be formed in a similarly high density.

SUMMARY

However, this inventor has found that when a fine hole pattern is formedby using a lithography technique, the contrast of an optical imageformed on a wafer is too low to provide a sufficient optical strengthfor image resolution. This is apt to lead to problems such as shallowfocus depth, defective piercing, and small lithography processingmargin. The inventor has also found that the occurrence of theseproblems is prominent particularly in regions where the hole density islow, for example, at bit-line contacts of a memory semiconductor device.

In one embodiment, there is provided a semiconductor device thatincludes a first interlayer film defining a plurality of contact holesarranged along a first direction. A plurality of contact plugs is filledin the contact holes, respectively. A second interlayer film is formedon the first interlayer film and has an opening to expose apredetermined region of the first interlayer film including a regionwhere the contact plugs are disposed. A plurality of interconnections isformed to extend across the opening and to be in contact with topsurfaces of the contact plugs, respectively. Each interconnectionextends in a second direction which is crossed to the first direction.

In another embodiment, there is provided a manufacturing method of asemiconductor device that includes: forming a plurality of contact plugsarranged in a first direction in a first interlayer film; forming asecond interlayer film on the first interlayer film and on the contactplugs; forming an opening in the second interlayer film to expose apredetermined region of the first interlayer film including a regionwhere the contact plugs are formed; forming a interconnection conductivefilm on the second interlayer film to bury the opening by theinterconnection conductive film; and patterning the interconnectionconductive film to form a plurality of interconnections which are incontact with the contact plugs, respectively, wherein eachinterconnection extends in the second direction being crossed to thefirst direction.

According to this invention, an opening is formed in an insulation filmformed on a plurality of contact plugs such that these contact plugs areexposed together in this opening. This makes it possible to make theprocessing margin larger in comparison with a case in which holes areformed in one-to-one relationship to contact plugs.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a plan view for explaining a configuration of a semiconductordevice according to a first embodiment of this invention;

FIGS. 2A and 2B are diagrams for explaining steps until formation of asecond interlayer film in a method of manufacturing the semiconductordevice of FIG. 1, FIG. 2A being a cross-sectional view taken along theline A-A′ in FIG. 1, FIG. 2B being a cross-sectional view taken alongthe line B-B′ in FIG. 1;

FIGS. 3A to 3C are diagrams for explaining a step of forming abit-line-contact forming groove subsequent to the steps shown in FIGS.2A and 2B, FIG. 3A being a cross-sectional view taken along the lineA-A′ in FIG. 1, FIG. 3B being a cross-sectional view taken along theline B-B′ in FIG. 1, FIG. 3C being a plan view showing the surroundingarea of the bit-line-contact forming groove shown in FIG. 1;

FIGS. 4A and 4B are diagrams for explaining a step of forming a secondconducting film subsequent to the step shown in FIGS. 3A to 3C, FIG. 4Abeing a cross-sectional view taken along the line A-A′ in FIG. 1, FIG.4B being a cross-sectional view taken along the line B-B′ in FIG. 1;

FIGS. 5A to 5C are diagrams for explaining a step of forming a bit-linecontact plug subsequent to the step shown in FIGS. 4A and 4B, FIG. 5Abeing a cross-sectional view taken along the line A-A′ in FIG. 1, FIG. 5B being a cross-sectional view taken along the line B-B′ in FIG. 1, FIG.5 C being a plan view showing the surrounding area of thebit-line-contact forming groove shown in FIG. 1;

FIGS. 6A and 6B are diagrams for explaining a step of forming a thirdconducting film and a bit-line hard mask film subsequent to the stepshown in FIGS. 5A to 5C, FIG. 6A being a cross-sectional view takenalong the line A-A′ in FIG. 1, FIG. 6B being a cross-sectional viewtaken along the line B-B′ in FIG. 1;

FIGS. 7A to 7C are diagrams for explaining a step of forming bit linessubsequent to the step shown in FIGS. 6A and 6B, FIG. 7A being across-sectional view taken along the line A-A′ in FIG. 1, FIG. 7B beinga cross-sectional view taken along the line B-B′ in FIG. 1, FIG. 7Cbeing a plan view showing the surrounding area of the bit-line-contactforming groove shown in FIG. 1;

FIGS. 8A and 8B are diagrams for explaining possible problemsencountered when the over-etching amount is insufficient duringformation of bit lines, FIG. 8A being a cross-sectional view taken alongthe line A-A′ in FIG. 1, FIG. 8B being a cross-sectional view takenalong the line B-B′ in FIG. 1;

FIGS. 9A and 9B are diagrams for explaining a step of formation of abit-line-contact forming groove and recess etching in a method ofmanufacturing a semiconductor device according to a second embodiment ofthis invention, FIG. 9A being a cross-sectional view taken along theline A-A′ in FIG. 1, FIG. 9B being a cross-sectional view taken alongthe line B-B′ in FIG. 1;

FIGS. 10A and 10B are diagrams for explaining a step of forming a secondconducting film subsequent to the step shown in FIGS. 9A and 9B, FIG.10A being a cross-sectional view taken along the line A-A′ in FIG. 1,FIG. 10B being a cross-sectional view taken along the line B-B′ in FIG.1;

FIGS. 11A and 11B are diagrams for explain a step of forming bit-linecontact plugs subsequent to the step shown in FIGS. 10A and 10B, FIG.11A being a cross-sectional view taken along the line A-A′ in FIG. 1,FIG. 11B being a cross-sectional view taken along the line B-B′ in FIG.1;

FIGS. 12A and 12B are diagrams for forming a step of forming a thirdconducting film and a bit-line hard mask film subsequent to the stepshown in FIGS. 11A and 11B, FIG. 12A being a cross-sectional view takenalong the line A-A′ in FIG. 1, FIG. 12B being a cross-sectional viewtaken along the line B-B′ in FIG. 1;

FIGS. 13A and 13B are diagrams for explain a step for forming bit linessubsequent to the step shown in FIGS. 12A and 12B, FIG. 13A being across-sectional view taken along the line A-A′ in FIG. 1, FIG. 13B beinga cross-sectional view taken along the line B-B′ in FIG. 1;

FIG. 14A and FIG. 14B are diagrams for explain steps after formation ofa first interlayer film until formation of a second interlayer film in amethod of manufacturing a semiconductor device according to a thirdembodiment of this invention, FIG. 14A being a cross-sectional viewtaken along the line A-A′ in FIG. 1, FIG. 14B being a cross-sectionalview taken along the line B-B′ in FIG. 1;

FIGS. 15A to 15C are diagrams for explain a step for forming abit-line-contact forming groove subsequent to the step shown in FIGS.14A and 14B, FIG. 15A being a cross-sectional view taken along the lineA-A′ in FIG. 1, FIG. 15B being a cross-sectional view taken along theline B-B′ in FIG. 1, FIG. 15C being a plan view showing the surroundingarea of the bit-line-contact forming groove shown in FIG. 1;

FIGS. 16A and 16B are diagrams for explain a recess etching stepsubsequent to the step shown in FIGS. 15A to 15C, FIG. 16A being across-sectional view taken along the line A-A′ in FIG. 1, FIG. 16B beinga cross-sectional view taken along the line B-B′ in FIG. 1;

FIGS. 17A and 17B are diagrams for explaining a step of forming a secondconducting film subsequent to the step shown in FIGS. 16A and 16B, FIG.17A being a cross-sectional view taken along the line A-A′ in FIG. 1,FIG. 17B being a cross-sectional view taken along the line B-B′ in FIG.1;

FIGS. 18A and 18B are diagrams for explaining a step of forming bit-linecontact plugs subsequent to the step shown in FIGS. 17A and 17B, FIG.18A being a cross-sectional view taken along the line A-A′ in FIG. 1,FIG. 18B being a cross-sectional view taken along the line B-B′ in FIG.1;

FIGS. 19A to 19C are diagrams for explaining a step of forming bit linessubsequent to the step shown in FIGS. 18A and 18B, FIG. 19A being across-sectional view taken along the line A-A′ in FIG. 1, FIG. 19B beinga cross-sectional view taken along the line B-B′ in FIG. 1, FIG. 19Cbeing a plan view showing the surrounding area of the bit-line-contactforming groove shown in FIG. 1;

FIGS. 20A and 20B are diagrams for explaining a step of forming a secondconducting film and a bit-line hard mask film in a method ofmanufacturing a semiconductor device according to a fourth embodiment ofthis invention, FIG. 20A being a cross-sectional view taken along theline A-A′ in FIG. 1, FIG. 20B being a cross-sectional view taken alongthe line B-B′ in FIG. 1;

FIGS. 21A and 21B are diagrams for explaining a step of forming bitlines subsequent to the step shown in FIGS. 20A and 20B, FIG. 21A beinga cross-sectional view taken along the line A-A′ in FIG. 1, FIG. 21Bbeing a cross-sectional view taken along the line B-B′ in FIG. 1; and

FIG. 22 is a plan view for explaining a configuration of a semiconductordevice according to a fifth embodiment of this invention.

DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposes.

FIG. 1 is a plan view for explaining a partial configuration of asemiconductor device (memory device) according to a first embodiment ofthe invention. FIG. 1 shows a state of the memory device in whichformation of bit lines serving as interconnections has been finished.

The shown memory device has an active region layer, a memory cell pluglayer, a bit-line-contact forming groove layer, a word line layer, and abit line layer. These layers are represented in FIG. 1 as active regions11, sets of memory cell plugs each consisting of a first memory cellplug 12 and a pair of second memory cell plugs 13, bit-line-contactforming grooves 14, word lines 15, and bit lines 16.

The active regions 11 are arranged to make a predetermined angle to thebit lines 16. A pair of transistors are formed in each of the activeregions 11 such that one of the source/drain regions is shared. Thismeans that there are formed, in each of the active regions 11, twotransistors having three source/drain regions.

Each of the first memory cell plugs 12 is formed on the source/drainregion located at the center of the three source/drain regions in eachof the active regions 11, and is connected to the corresponding bit line16. A pair of second memory cell plugs 13 are formed on the source/drainregions located at the opposite ends of each of the active region 11,and connected to electrodes not shown. When the memory device is a DRAMdevice, the electrodes to which the second memory cell plugs 13 areconnected are capacitor electrodes.

Each of the bit-line-contact forming grooves 14 is an opening formed ina second interlayer film to be described later, and is formed to cover aplurality of first memory cell plugs 12 arranged along a direction inwhich the word lines 15 are extended. In FIG. 1, each set of firstmemory cells is composed of three first memory cells, and an opening isformed to cover each set of the first memory cells.

The word lines 15 are formed to extend in a vertical direction as viewedin the drawing, while the bit lines 16 are formed to extend orthogonallyto the word lines and in a transverse direction as viewed in thedrawing. Each of the bit lines 16 is connected in common to a pluralityof first memory cell plugs 12 adjacent to each other with respect to thedirection the bit line 16 is extended and belong to different sets ofmemory cell plugs.

A method of manufacturing the semiconductor device shown in FIG. 1 willbe described with reference to FIGS. 2A and 2B through FIGS. 7A to 7C.FIGS. 2A to 7A are cross-sectional views taken along the line A-A′ inFIG. 1, while FIGS. 2B to 7B are cross-sectional views taken along theline B-B′ in FIG. 1. FIGS. 3C, 5C and 7C are plan views showing thesurrounding area of the bit-line-contact forming groove 14.

Firstly, as shown in FIGS. 2A and 2B, there are formed, on a p-typesubstrate (semiconductor substrate) 21, element isolation regions 22,word lines 15 each composed of a gate insulation film 23, a gateconducting film 24, a mask nitride film 25 and a spacer nitride film 26,and n-type source/drain regions 27 forming transistors.

Next, a first interlayer film 28 is formed as a first insulation film.The first interlayer film 28 may be, for example, a silicon oxide film,a BPSG (Boron-doped Phospho-Silicate Glass) film, or SOG (Spin On Glass)film.

Subsequently, memory cell contact holes are opened in the firstinterlayer film 28 as contact holes to reach the source/drain regions 27on the substrate 21. Then, the memory cell plugs 12 (and 13) formed fromthe first conducting film are formed in the memory cell contact holes asfirst contact plugs. A phosphorus-doped silicon film, for example, maybe used as the first conducting film. Alternatively, the firstconducting film may be formed by growing a Ti film and a TiN film asbarrier metal films and then growing a W film.

The memory cell plugs 12 (and 13) are formed by forming the firstconducting film to fill the memory contact holes, and then removing thefirst conducting film located on the first interlayer film 28 by a CMPmethod or the like. Alternatively, the memory cell plugs 12 (and 13) maybe formed by etching back the first conducting film using an etchingtechnique. The top surfaces of the memory cell plugs 12 (and 13) areformed to be substantially flush with the top surface of the firstinterlayer film 28 as viewed perpendicularly to the principal surface ofthe substrate 21 (in a vertical direction in FIG. 2).

Then, a second interlayer film 29 is formed as a second insulation filmon the first interlayer film 28 and the memory cell plugs 12 (and 13).The second interlayer film 29 may be formed, for example, by a siliconoxide film, a BPSG film, or a SOG film.

Next, as shown in FIGS. 3A, 3B and 3C, the bit-line-contact forminggroove 14 is formed as an opening in the second interlayer film 29. Thebit-line-contact forming groove 14 is formed to expose the surface of aplurality of (three, in this example) first memory cell plugs 12 and thesurface of the first interlayer film 28 surrounding these first memorycell plugs. In other words, the bit-line-contact forming groove 14 isformed so as to expose a predetermined region including a region of thefirst interlayer film 28 where the first memory cell plugs 12 areformed. This means that this predetermined region covers a plurality offirst memory cell plugs 12 arranged adjacent to each other along adirection in which the word lines 15 are extended.

Formation of the bit-line-contact forming groove 14 can be performed byforming a resist pattern of the bit-line-contact forming groove 14 onthe second interlayer film 29 using a lithography technique, and thenetching the second interlayer film 29 using the formed resist pattern asa mask. The resist pattern is then removed.

Next, a pretreatment is carried out to clean the surface of the exposedfirst memory cell plugs 12 to prepare for formation of bit-line contactplugs connected to the exposed first memory cell plugs 12. Thispretreatment is generally performed by etching. However, as thesemiconductor devices are miniaturized, the sizes of holes and groovesto be treated are also miniaturized, making it difficult to perform thepretreatment. Further, as the contact size is miniaturized, reduction ofcontact resistance is important, and thus sufficient cleaning isimperative. Under such background circumstances, etching must beperformed sufficiently as the pretreatment.

A wet pretreatment method may be used as a cleaning method for thepretreatment. A solution of diluted hydrofluoric acid (HF:water=1:200)is used as chemical solution, and etching is performed in an amountsufficient to etch away a thickness of 3 nm of the thermal oxidationfilm. If there adheres a 1-nm-thick natural oxide film, the requiredetching amount will be 100 to 200% over the amount required for removingthe natural oxide film. When using the solution of diluted hydrofluoricacid (HF:water=1:200), the required etching time is about two minutes.This etching amount also depends on the surface condition of the firstmemory cell plugs 12. In some cases, further cleaning by a greateramount of etching or cleaning with different type of chemical solutionmay become necessary.

The above-described cleaning step (pretreatment step) not only cleansthe surface of the first memory cell plugs 12 but also etches away apart of the first interlayer film 28 and second interlayer film 29. Thisreduces the thickness of the second interlayer film 29. The firstinterlayer film 28 is etched down in the bit-line-contact forming groove14. As a result, the level of the top surface of the first interlayerfilm 28 in the bit-line-contact forming groove 14 becomes lower than thelevel of the top surfaces of the first memory cell plugs 12.Specifically, a recessed portion is formed in the first interlayer film28 around the first memory cell plugs 12, and hence the upper part ofthe first memory cell plugs 12 protrudes out of the surface of the firstinterlayer film surrounding the same. The top surface of the part of thefirst interlayer film 28 located within the bit-line-contact forminggroove 14 becomes lower in level than the top surface of the region ofthe first interlayer film 28 where the bit-line-contact forming groove14 is not formed (i.e. the boundary between the first interlayer film 28and the second interlayer film 29) as viewed perpendicularly to theprincipal surface of the substrate 21.

It should be noted that the amount of the first interlayer film 28etched away by this pretreatment is five to ten times greater incomparison with the case of a thermal oxidation film. In the case of asilicon oxide film, for example, about 20 nm of the film is etched away.This is not only because the structure is miniaturized but also becausethe etching resistance of the interlayer insulation film is deteriorateddue to use of a low-temperature rapid thermal treatment such as RTP(Rapid Thermal Processing) (for example, ten minutes at 750° C.) forthermal treatment of the interlayer insulation film in order to reducethe thermal load to the transistors.

In the pretreatment, dry cleaning may be used as the cleaning method, inplace of the wet pretreatment. In this case, HF gas is used. The drycleaning is more advantageous than the wet pretreatment method in thatit exhibits higher cleaning effect when cleaning minute holes or thelike. Like the wet etching, the etching amount is set to a valuecorresponding to 100 to 200% over the amount required for removing thenatural oxide film.

Next, an interconnection conducting film for forming interconnections isformed. In this example, a second conducting film and a third conductingfilm are used as the interconnection conducting film.

Firstly, in order to form a bit-line contact plug in each of thebit-line-contact forming grooves 14 cleaned as described above, a secondconducting film 41 is formed as shown in FIGS. 4A and 4B. Thebit-line-contact forming grooves 14 are thus filled with the secondconducting film 41. The second conducting film 41 may be a layered filmformed by sequentially depositing a Ti film, a TiN film, and a W film.The film formation may be carried out by using a CVD method. If there isno problem in terms of contact resistance, impurity doped silicon or thelike may be used for the second conducting film 41.

The second conducting film 41 is then polished by using a CMP methodsuch that a portion of the second conducting film 41 buried in thebit-line-contact forming groove 14 is left unremoved. As a result, asshown in FIGS. 5A, 5B and 5C, a bit-line contact plug 51 buried in thebit-line-contact forming groove 14 is formed as a second contact plug.The top surface of the second interlayer film 29 is exposed.

Next, as shown in FIGS. 6A and 6B, a third conducting film 61 forforming the bit lines 16 serving as interconnections is formed, and abit-line hard mask film 62 is formed on the third conducting film 61.

The third conducting film 61 can be formed, for example, by sequentiallydepositing a TiN film and a W film using a sputtering method.Alternatively, the third conducting film 61 may be formed by using a WSifilm, a WSi polycide film (WSi/doped silicon), or the like. The bit-linehard mask film 62 may be formed of a silicon nitride film by using aplasma CVD method.

Next, a resist mask of a bit line pattern in which bit lines arearranged to pass over the first memory cell plugs 12 and to pass acrossthe bit-line-contact forming grooves 14 is formed by using aphotolithography technique. Using this mask, the bit-line hard mask film62 and the third conducting film 61 are sequentially etched to exposethe surface of the second interlayer film 29. Further, the bit-linecontact plug 51 (the second conducting film 41) buried in thebit-line-contact forming groove 14 is etched to expose the surface ofthe first interlayer film 28 on the bottom of the bit-line-contactforming groove 14. The etching of the third conducting film 61 and thesecond conducting film 41 may be performed by using a gas containing Cl₂or the like. As shown in FIGS. 7A, 7B and 7C, the bit-line contact plug51 is patterned according to the pattern of the bit lines 16, anddivided to correspond to the respective first memory cell plugs 12.Thus, a plurality of the first memory cell plugs 12 exposed in the samebit-line-contact forming groove 14 are electrically isolated from eachother. As a result, the bit lines 16 are formed, each being formed ofthe third conducting film 61 and connected to the first memory cell plug12 via the second conducting film 41 (i.e. the bit-line contact plug51). In other words, the bit lines 16 provide a plurality ofinterconnections each of which is formed to pass across the opening andto be electrically connected to the top surfaces of the correspondingplurality of first memory cell plugs. The interconnections are eachformed to extend from the recessed portion in the first insulation film,via the opening in the second insulation film, up to the top surface ofthe second insulation film.

According to this embodiment, as described above, bit-line contacts areprovided by forming grooves each covering a plurality of first memorycell plugs, instead of forming holes in correspondence with respectivefirst memory cell plugs. This makes it possible to increase thelithography margin.

If holes are formed as is conventionally done, it is desired to open theentire area of the top surface of the first memory cell plug in order toincrease the contact area between the first memory cell plug and thebit-line contact plug. In this case, the distance between the holes isshort, and hence the width of the resist pattern defining the distancebetween the holes becomes so small that the resist pattern may be causedto partially disappear by dry etching during formation of the holes andadjacent holes may be joined (short-circuited) to each other. Accordingto this embodiment of the invention, in contrast, grooves are formedsuch that each groove covers a plurality of first memory cell plugswhich are adjacent to each other and the bit-line contact plugs areburied in the grooves, so that the bit-line contact plugs are alsoetched when patterning the bit lines. Thus, according to thisembodiment, the bit-line contacts are formed in a self-aligned manner,and hence the risk short circuit is eliminated.

Further, according to this first embodiment, a sufficient pretreatmentis performed before depositing the second conducting film to form thebit-line contact plugs, so that contacts with low resistance can beformed. In addition, a recessed portion is formed in the firstinterlayer film by this pretreatment so that the first memory cell plugsproject out. Accordingly, the contact area between the first memory cellplug and the bit-line contact plug can be increased, and contacts withlow resistance can be provided.

As described above, the first embodiment of the invention enablesformation of minute contacts.

A second embodiment of this invention will now be described.

As described above, in the semiconductor device according to the firstembodiment, the first memory cell plugs 12 are configured to project outfrom the first interlayer film 28. The second conducting film 41 isdeposited between these first memory cell plugs 12 and later removed byetching. As semiconductor devices are miniaturized further, the distancebetween the first memory cell plugs 12 will be decreased further. Thenthe over-etching amount must be increased in order to remove thedeposited second conducting film 41. In particular, when the secondconducting film 41 is formed by barrier metal films such as a TiN film,a Ti film, and a WN film, which have low etching rate, the over-etchingrate will need to be further increased in order to remove the filmscompletely without leaving residues. The increased over-etching amountwill lead to increased thickness of the bit-line hard mask film 62,constituting an obstructive factor to miniaturization of thesemiconductor device.

On the other hand, if the over-etching amount is not sufficient,residues 81 will be left between the first memory cell plugs 12, asshown in FIGS. 8A and 8B, possibly causing short-circuit.

Therefore, a semiconductor device according to the second embodimentemploys a configuration which prevents formation of residues whenetching away the second conducting film 41, and facilitates patterningof interconnections. Below, a method of manufacturing a semiconductordevice according to the second embodiment will be described, while alsodescribing a configuration thereof.

Like the first embodiment, the semiconductor device according to thesecond embodiment is a memory device having a configuration as shown inFIG. 1. The manufacturing steps of this memory device are the same asthe first embodiment until the state shown in FIGS. 3A and 3B isattained.

After the bit-line-contact forming groove 14 has been formed as shown inFIGS. 3A and 3B, the first memory cell plugs 12 (first conducting film)are recess-etched as shown in FIGS. 9A and 9B. This etching is performedsuch that the top surfaces of the first memory cell plugs 12 are lowerin level than the top surface of the first interlayer film 28 by about50 nm at the bottom of the bit-line-contact forming groove 14 (theinterface between the first interlayer film 28 and the second interlayerfilm 29), as viewed perpendicularly to the principal surface of thesubstrate 21. At the same time, the recess etching is performed suchthat the level of the top surfaces of the first memory cell plugs 12does not become too low, and the top surfaces the first memory cellplugs are at a level 100 nm or more above the surface of the substrate.This is necessary because the substrate 21 might be etched by thesubsequent etching for formation of the bit lines 16.

Next, as shown in FIGS. 10A and 10B, a second conducting film 41 isformed. In the same manner as in the first embodiment, a pretreatment(cleaning) is performed sufficiently prior to the formation of thesecond conducting film 41. This pretreatment reduces the thickness ofthe second interlayer film 29, and forms a recessed portion in the firstinterlayer film 28 within the bit-line-contact forming groove 14. Theabove-described recess etching process for lowering the level of the topsurfaces of the first memory cell plugs is performed such that, in thestate after the pretreatment, the level h2 of the top surfaces of thefirst memory cell plugs 12 is lower than the level h1 of the principalsurface of the first interlayer film 28 located between the first memorycell plugs 12. For example, if the principal surface of the firstinterlayer film 28 is set back by the pretreatment by 20 to 30 nm, thetop surfaces of the first memory cell plugs 12 can be made lower inlevel than the level of the principal surface of the first interlayerfilm 28 by 20 to 30 nm by recess-etching the top surfaces of the firstmemory cell plugs 12 by 50 nm.

After that, the same steps as in the first embodiment are performed.

Specifically, the second conducting film 41 is polished by a CMP methodto expose the second interlayer film 29 and to form a bit-line contactplug 51 buried in the bit-line-contact forming groove 14 as shown inFIGS. 11A and 11B.

Then, as shown in FIGS. 12A and 12B, a third conducting film 61 and abit-line hard mask film 62 to form bit lines 16 are sequentially formed.

Subsequently, using a resist mask of bit line pattern, the bit-line hardmask film 62, the third conducting film 61, and the bit-line contactplugs 51 are etched (patterned) to form bit lines 16 as shown in FIGS.13A and 13B.

According to this second embodiment, the first memory cell plugs 12 arerecessed with respect to the first interlayer film 28. Therefore, thearea of the side walls of the first memory cell plugs 12 in contact withthe second conducting film 41 (bit-line contact plug 51) is small. As aresult, the second conducting film 41 is prevented from being left in aspacer-like form on the side walls of the first memory cell plugs 12when patterning the bit-line contact plug 51. Thus, this secondembodiment is able to provide a configuration having an enhanced effectof preventing the short circuit between the adjacent bit lines.

Further, according to the second embodiment, the second conducting film41 formed in narrow gaps such as those between the first memory cellplugs 12 need not be removed, and hence the over-etching amount can bereduced. According to the second embodiment, therefore, the thickness ofthe bit-line hard mask film 62 can be reduced, and a configurationdesirable for miniaturization of the semiconductor device can beobtained.

Although the second conducting film 41 may be left unremoved on the partin the recessed portion of the first memory cell plug 12 where no bitline is formed, it does not pose a problem.

Next, referring to FIGS. 14A and 14 b through 19A to 19C, asemiconductor device according to a third embodiment of this inventionwill be described.

While in the first and second embodiments described above, the firstinterlayer film 28 exists also on the word lines 15, the firstinterlayer film 28 does not exist on the word lines 15 in this thirdembodiment.

More specifically, the manufacture of the semiconductor device accordingto the third embodiment is performed in the same manner as in the firstembodiment until the step of depositing the first interlayer film 28.

After depositing the first interlayer film 28 on the word lines 15, thefirst interlayer film 28 is polished away until the top of the wordlines 15, that is, the mask nitride film 25 is exposed. Employing a CMPmethod, the polishing can be performed while using the mask nitride film25 located in the upper part of the word lines 15 as a stopper. Then,the first memory cell plugs 12 are formed in the same manner as in thefirst embodiment. As shown in FIGS. 14A and 14B, there are formed themask nitride film 25 for forming the upper part of the word lines 15,the spacer nitride film 26, and the second interlayer film 29 in contactwith the top surfaces of the first memory cell plugs 12.

Next, as shown in FIGS. 15A, 15B and 15C, the bit-line-contact forminggroove 14 is opened in the second interlayer film 29. There are exposed,in the bit-line-contact forming groove 14, the top surfaces of the firstmemory cell plugs 12, the first interlayer film 28 surrounding the firstmemory cell plugs 12, the mask nitride film 25 and the spacer nitridefilm 26.

After that, the same steps as in the second embodiment are performed.

Specifically, the top surfaces of the first memory cell plugs 12 arerecess-etched as shown in FIGS. 16A and 16B.

Then, the inside of the bit-line-contact forming groove 14 is cleaned bya pretreatment process, and a second conducting film 41 is formed tofill the bit-line-contact forming groove 14 as shown in FIGS. 17A and17B.

Subsequently, as shown in FIGS. 18A and 18B, the second conducting film41 is polished to expose the second interlayer film 29, whereby abit-line contact plug 51 is formed in the bit-line-contact forminggroove 14.

Finally, as shown in FIGS. 19A and 19B, a third conducting film 61 and abit-line hard mask film 62 are sequentially formed, and the formed filmsare patterned to form bit lines 16.

As described above, the semiconductor device according to the thirdembodiment is manufactured.

According to the third embodiment, the top surface of the firstinterlayer film 28 is made flush with the top surface of the masknitride film 25 in the upper part of the word lines 15. Therefore, theuniformity in each chip can be improved in terms of thickness of thefirst interlayer film 28.

Further, according to this embodiment, the height of the first memorycell plugs 12 can be reduced, and thus the contact resistance can bereduced.

Next, referring to FIGS. 20A and 20B, and FIGS. 21A and 21B, a fourthembodiment of this invention will be described.

While description of the first to third embodiments has been made of acase in which the second conducting film and the third conducting filmare used as an interconnection conducting film, this fourth embodimentuses only the second conducting film as the interconnection conductingfilm. This means that the second conducting film which is the materialof the bit-line contact plugs is directly used to form interconnections.

A manufacturing method of the semiconductor device according to thisembodiment is the same as any one of the first to third embodimentsuntil the step of forming the second conducting film. The followingdescription will be made of a case in which the method is the same as inthe second embodiment.

After forming the second conducting film 41, that is, after the stateshown in FIGS. 10A and 10B has been obtained, a bit-line hard mask film62 is deposited as shown in FIGS. 20A and 20B.

Next, using a resist mask having a bit line pattern, the bit-line hardmask film 62 and the second conducting film 41 are patterned to form bitlines 16 as shown in FIG. 21A and FIG. 21B.

According to the fourth embodiment, as described above, the bit lines 16can be formed without forming a third conducting film.

Thus, this fourth embodiment makes it possible to omit the step offorming the bit-line contact plug (the step shown in FIGS. 5A to 5C,FIGS. 11A and 11B, or FIGS. 18A and 18B) and the step of forming thethird conducting film, providing advantages that the manufacturing stepscan be simplified and the manufacturing cost can be reduced.

Next, a semiconductor device according to a fifth embodiment of thisinvention will be described.

Although the description of the first to fourth embodiments has beenmade of a case in which the semiconductor device is a memory device,this invention is applicable to semiconductor devices other than memorydevices. The semiconductor device according to the fifth embodiment isassumed to be a common integrated circuit.

FIG. 22 is a plan view for explaining a schematic configuration of asemiconductor device according to the fifth embodiment, showing a statein which the step of forming interconnections has been finished.

The shown semiconductor device has an active region layer, a gateelectrode layer, a first contact plug layer, a second contact forminggroove layer, and a wiring layer, forming a plurality of (four, in thisexample) transistors Tr1 to Tr4 arranged in an array. In FIG. 22, theselayers are represented as active regions 101, gate electrodes 102, firstcontact plugs 103, second contact forming grooves 104, andinterconnections 105, respectively.

Second contact plugs (not shown) are formed on top of the first contactplugs 103. A second contact forming groove 104 is formed in aninterlayer insulation film formed on the first contact plugs 103, thetop surfaces of the first contact plugs 103 are exposed, and then thesecond contact plug is formed thereon. The interconnections 105 areelectrically connected to the first contact plugs 103 via the secondcontact plug. Each of the interconnections 105 is formed to electricallyconnect a plurality of first contact plugs 103 arranged adjacent to eachother in a transverse direction as viewed in the drawing.

The semiconductor device according to this fifth embodiment can bemanufactured in the same manufacturing method of the semiconductordevice according to the first to fourth embodiments. The gate electrodes102, the first contact plugs 103, the second contact forming grooves104, and the interconnections 105 in this fifth embodiment correspondingto the word lines 15, the memory cell plugs 12, the bit-line-contactforming grooves 14, and the bit lines 16, respectively.

According to this embodiment, the second contact forming grooves 104each covering a plurality of (four, in this example) first contact plugare provided instead of providing holes in correspondence with therespective first contact plugs 103. Accordingly, even if the firstcontact plugs 103 are integrated or arranged at a high density, thelithography process to be performed on the second contact plugs can beperformed easily.

Thus, the application of this invention it not limited to memorydevices, but the invention is widely applicable to semiconductor deviceshaving a configuration in which an insulation film is formed on contactplugs and interconnections are formed to be connected to the topsurfaces of the contact plugs.

Although this invention has been described in conjunction with a severalpreferred embodiments thereof, this invention is not limited to theforegoing embodiments but may be modified in various other mannerswithin the scope of the appended claims. For example, an insulation filmmade of a material other than those mentioned above may be used as thefirst and second interlayer films. Likewise, a conducting film made of amaterial other than those mentioned above may be used as the first,second and third conducting films. In this case, a barrier metal may beused if appropriate. Further, the number of contact plugs exposed ineach contact forming groove is at least two or more. In this case, thecontact forming grooves can be formed such that each contact forminggroove corresponds to each row of contact plugs arranged along apredetermined direction.

1. A semiconductor device comprising: a first interlayer film defining aplurality of contact holes arranged along a first direction; a pluralityof contact plugs filled in the contact holes, respectively; a secondinterlayer film formed on the first interlayer film and having anopening to expose a predetermined region of the first interlayer filmincluding a region where the contact plugs are disposed; and a pluralityof interconnections formed to extend across the opening and to be incontact with top surfaces of the contact plugs, respectively, whereineach interconnection extends in a second direction being crossed to thefirst direction.
 2. The semiconductor device as claimed in claim 1,wherein the first interlayer film includes a portion which is etcheddown from a surface of the first interlayer film within the opening. 3.The semiconductor device as claimed in claim 1, wherein the top surfacesof the contact plugs are lower in level than a interface between thefirst interlayer film and the second interlayer film.
 4. Thesemiconductor device as claimed in claim 1, wherein the first interlayerfilm is disposed on a semiconductor substrate; and the semiconductordevice further comprises: a recessed portion formed in the region of thefirst insulation film exposed by the opening, the recessed portionincluding a top surface which is lower than a level of a top surface ofa region of the first insulation film where the opening is not formed.5. The semiconductor device as claimed in claim 4, wherein the topsurface of the recessed portion in the first insulation film includes apart which is higher in level than the top surfaces of the contactplugs.
 6. The semiconductor device as claimed in claim 4, wherein theinterconnections are formed to extend from the recessed portion in thefirst insulation film via the opening in the second insulation film upto a top surface of the second insulation film such that theinterconnections pass across the opening and are connected to the topsurfaces of the respective contact plugs.
 7. The semiconductor device asclaimed in claim 4, comprising a plurality of sets of the contact plugs,the opening being formed in correspondence with each set thereof.
 8. Thesemiconductor device as claimed in claim 7, wherein each of theinterconnections is connected to the top surfaces of the contact plugsbelonging to different sets.
 9. The semiconductor device as claimed inclaim 4, further comprising a wiring line disposed on the semiconductorsubstrate, wherein the top surfaces of the contact plugs are lower inlevel than a top surface of the wiring line.
 10. A manufacturing methodof a semiconductor device, comprising: forming a plurality of contactplugs arranged in a first direction in a first interlayer film; forminga second interlayer film on the first interlayer film and on the contactplugs; forming an opening in the second interlayer film to expose apredetermined region of the first interlayer film including a regionwhere the contact plugs are formed; forming a interconnection conductivefilm on the second interlayer film to bury the opening by theinterconnection conductive film; and patterning the interconnectionconductive film to form a plurality of interconnections which are incontact with the contact plugs, respectively, wherein eachinterconnection extends in the second direction being crossed to thefirst direction.
 11. The manufacturing method as claimed in claim 10,wherein a part of the first interlayer film exposed in the opening isremoved before forming the interconnection conductive film on the secondinterlayer film.
 12. The manufacturing method as claimed in claim 11,wherein the part of the first interlayer film exposed in the opening isremoved by using a solution of diluted hydrofluoric acid.
 13. Themanufacturing method as claimed in claim 10, wherein an upper portion ofeach of the contact plugs is removed before forming the interconnectionconductive film on the second interlayer film such that a top surface ofeach of the contact plugs becomes lower in level than an interfacebetween the first interlayer film and the second interlayer film. 14.The manufacturing method as claimed in claim 10, wherein: the contactplugs are formed by a first conducting film; and forming theinterconnection conductive film comprises: forming a second conductingfilm to fill the opening and to be in contact with the contact plugs;and forming a third conducting film on the second conducting film. 15.The manufacturing method as claimed in claim 10, wherein the openingpasses through the second insulation film and exposes top surfaces ofthe contact plugs and an area of the first insulation film surroundingthe contact plugs.
 16. The manufacturing method as claimed in claim 15,further comprising: etching down a surface area of the first insulationfilm exposed in the opening to form a recessed portion in the firstinsulation film, wherein the interconnection conducting film remains inthe recessed portion.
 17. The manufacturing method as claimed in claim16, further comprising: removing an upper portion of each of the firstcontact plugs between forming the opening in the second insulation filmand etching down the surface area of the first insulation film exposedin the opening.
 18. The manufacturing method as claimed in claim 17,wherein a top surface of the first insulation film in the recessedportion is partially higher in level than the top surfaces of thecontact plugs after removing the upper portion of each of the contactplugs.
 19. The manufacturing method as claimed in claim 14, whereinforming of the interconnections is performed by sequentially patterningthe third conducting film and the second conducting film.
 20. Themanufacturing method as claimed in claim 14, further comprising:removing the second conducting film on a top surface of the secondinterlayer film to remain the second conducting film in the openingbefore forming the third conducting film on the second conducting film.